Conventional non-pipelined dynamic random access memories (DRAMs) perform data transfers in sequence. That is, when a read or write command is received and an address is made available, the data transfer, either read or write, is performed in its entirety before another command is accepted. Consequently, subsequent commands are delayed by the entire duration of the original data transfer. Because data transfers typically involve several steps and each step takes time, the overall time to perform the original data transfer may be significant. For example, for a read, the control logic of the DRAM must decode the command and the address, provide signals, such as the row address select signal RAS, and column address select signal CAS, perform precharge and equalization, address the memory array, allow time for sense amplifiers to develop signals, and transfer data from the sense amplifiers to output registers. Subsequent commands must wait until these operations are completed before they are accepted by the DRAM. Consequently, either the clock speed of the DRAM must be sufficiently slow to allow the original data transfer to be completed before a subsequent command is provided, or a dummy command, such as no-operation command NO-OP, must be provided at all clock edges until the data transfer is complete.
To reduce the amount of delay imposed in sequential data transfer operations, DRAMs can be "pipelined." In pipelining, each of the abovedescribed steps is performed according to a specific timing sequence. For example, when the original data transfer progresses from a first step (e.g., command decode and address decode) to a second step (e.g., read data), a second data transfer progresses to the first step (command and address decode). Thus, the control logic can begin decoding the second command and an address decoder can begin decoding the second address while the data from the original data transfer is being read from or written to the memory array.
To control the flow of data through a pipelined DRAM, commands and data are transferred synchronously. In synchronous operation, the timing sequence is established relative to leading edges of a clock signal. At fixed times relative to the leading edges, commands are read by the control logic, addresses are provided at an address input, signals are developed on input and output lines of the memory array, and data is made available for reading or writing at a data bus.
In synchronous read operations, an output of data on the data bus results from a command and an address received at a preceding leading edge of the clock. The delay in number of clock cycles between the arrival of the read command at the input to the control logic and the availability of data at the data bus is the "latency" of the pipelined DRAM. If the output data is available by the second leading edge of the clock following the arrival of the read command, the device is described as a two latency DRAM. If the data is available at the third leading edge of the clock following the arrival of the read command, the device is a three latency DRAM.
In conventional pipelined DRAMs, latency is only imposed for read operations. In write and block write operations, write and block write commands are supplied simultaneously with data at the data bus and transferred to the memory array as quickly as possible. Typical pipelined DRAMs may thus be described as having no write latency. Nevertheless, write and block write operations may take more than one clock period. In such cases, data from the write or block write may require the data bus for more than one leading edge of the clock. Consequently, a no operation command NO-OP may be required to prevent data collision after a write or block write commands.
Conventionally, control logic and data paths within two latency and three latency DRAMs are optimized for the particular latency of the device. By accurately controlling the timing of each step of the data transfer operation, decoded addresses, data and enabling signals arrive at the memory array substantially simultaneously. In response, signal development at the sense amplifiers begins at a prescribed time. Because the time at which data is to be output is determined by the latency (2 or 3 clock periods), the timing of signal development at the sense amplifiers can be optimized. Conversely, if the time necessary for signal development is known, the clock speed can be optimized for the amount of time necessary to perform all of the steps of the data transfer. In such pipelined DRAMs, the time period in which the data bus and address bus are occupied can be controlled accurately and the time at which the data bus and address bus are available for subsequent addresses and data is known. By tightly controlling the timing of signals on the address, command and data buses, the speed of data transfer through the DRAM can be optimized and data and command collisions can be minimized.
The timing requirements for two latency and three latency operation may differ. Therefore, devices are typically optimized for either two latency or three latency operation. Because three latency operation allows an additional clock cycle between the acceptance of a command and the actual transfer of data from the memory array, the clock speed of three latency devices is typically higher than for two latency devices.